1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a buried bit line and a method for fabricating the same.
2. Description of the Related Art
As the design rule parameters of semiconductor devices shrink and the cell sizes decrease, difficulties in the manufacturing process significantly increases (for example, in the 8F2 or 6F2 cell structure, where F is the minimum feature size. Furthermore, a channel margin is degraded by a corresponding reduction in gate length.
In order to address such features, a method for fabricating a semiconductor substrate, where a vertical transistor is formed over the semiconductor substrate has been developed. Exemplary structures formed by such a method include a vertical channel transistor using a pillar as a channel, where the pillar extends in a vertical direction with respect to the surface of the semiconductor substrate. Since the vertical channel transistor occupies a small horizontal area, the cell size may be reduced. Here, since the gate and channel of the vertical channel transistor are formed in a vertical direction, the vertical channel transistor may be implemented in the 4F2 cell structure.
When the vertical channel transistor using a pillar is used as a cell transistor of a memory device, one side of a junction becoming a source or drain is connected to a bit line, and the other side of the junction is connected to a capacitor. In general, since the capacitor is disposed over the cell transistor, the capacitor is connected to the top of the pillar, and the bit line is connected to the bottom of the pillar. The bit line is buried in a trench between pillars, and is thus referred to as a buried bit line.
In order to connect the bit line and one side of the junction, a sidewall of the pillar is exposed. This process is referred to as a single-side-contact (SSC) process or one-side contact (OSC) process. Hereafter, the process is referred to as the SSC process. The source formed in the pillar is exposed by the SSC process, and the buried bit line is electrically connected to the exposed source.
FIG. 1A illustrates a conventional buried bit line. FIG. 1B illustrates features of the conventional buried bit line.
Referring to FIG. 1A, a plurality of pillar structures isolated by trenches 15 are formed in a semiconductor substrate 11. Each of the pillar structures includes a body 12, a pillar 13 formed over the body 12, and a hard mask layer 14 formed over the pillar 13.
An insulation layer 16 is formed on the sidewalls of the pillar structure and the surface of the trench 15. The insulation layer 16 has an opening formed by using the OSC process. The opening opens any one sidewall of the body 12. A buried bit line 17 is formed to partially fill the trench 15. The buried bit line 17 is connected to the body 12 through the opening. The buried bit line 17 is connected to one of two adjacent bodies 12. A first junction 18 is formed in the body 12 so as to be contacted with the buried bit line 17, and a second junction 19 is formed over the pillar 13 so as to contact a capacitor. The first and second junctions 18 and 19 serve as source/drain regions of the vertical channel transistor.
In FIG. 1A, the buried bit line 17 is electrically connected to the first junction 18. In order to form the first junction 18, the trench 15 is gap-filled with doped polysilicon, and annealing is subsequently performed. The first junction 18 is formed before the buried bit line 17 is formed. According to the above description, the conventional semiconductor device has a body-tied structure in which the inside of the body 12 is locally doped to form the first junction 18. In the body-tied structure, the pillar 13 having a channel formed therein is connected to the body 12.
In the body-tied structure, however, since it is difficult to control thermal diffusion of a dopant, a floating-body structure is likely formed. For example, as illustrated in FIG. 1B, when the dopant is excessively diffused, the first junction 18A may be diffused to the other sidewall of the body 12. In this case, the body 12 may float with respect to the channel.
Furthermore, since the OSC process for forming the opening is complex and difficult to perform due to process limits caused by a reduction in critical dimension, mass production becomes difficult.